Sebastian Eckl

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Foto von Sebastian Eckl

Sebastian Eckl, M.Sc.

Technische Universität München

Informatik 13 - Professur für Vernetzte Rechensysteme - (Prof. Baumgarten)

Postadresse

Postal:
Boltzmannstr. 3
85748 Garching b. München

Lehre

Betreute Abschlussarbeiten

2019:

  • Extending L4 Fiasco.OC/Genode by Support for Heterogeneous Multi-Core Architectures (ARM big.LITTLE), IDP, 06/2019
  • Development of an Autonomous Parking application for L4 Fiasco.OC/Genode utilizing Microsoft AirSim and Matlab Simulink, Master's Thesis, 06/2019
  • Development of an Automotive Testbed for Migration of Software Components at Runtime, IDP, 05/2019
  • Titel N/A, BMW, Master's Thesis, 05/2019
  • Deep Learning Based Lane Detection in Driving Simulator Data with OpenCV on Android, Master's Thesis, 05/2019
  • Comparison of heuristic and deep learning based schedulability analysis approaches for migration of software components during runtime, Master's Thesis, 05/2019
  • Extension of L4 Fiasco.OC/Genode by a Multicore-based Checkpoint/Restore Mechanism, Bachelor's Thesis, 04/2019
  • Deep Learning Based Schedulability Analysis for Migration of Software Components at Runtime, Master's Thesis, 03/2019
  • Android-based Camera-supported Adaptive Cruise Control and Autonomous Overtaking Utilizing Driving Simulator Data with OpenCV, Bachelor's Thesis, 02/2019
  • Extending the RISC-V Memory Management Unit by Support for a Real-Time Capable Checkpoint/Restore Mechanism, Bachelor's Thesis, 02/2019
  • Extension of an Existing Hybrid Simulator Testbed by a Robotic/Industrial Automation Scenario, Bachelor's Thesis, 02/2019
  • Evaluation of the Microkernels L4 Fiasco.OC and seL4 using the Example of a Checkpoint/Restore Component to be ported, Master's Thesis, 02/2019
  • Performance Optimization of Shared Memory and Redundant Memory based Checkpoint/Restore Mechanisms for L4 Fiasco.OC/Genode, Master's Thesis, 02/2019
  • Optimization of a real-time capable Checkpoint/Restore mechanism for L4 Fiasco.OC/Genode by hardware-assisted memory tracing and copying, Master's Thesis, 01/2019

2018:

  • Optimization of a real-time capable Checkpoint/Restore mechanism by FPGA-based memory tracing and copying, IDP, 12/2018
  • Optimization of a real-time capable Checkpoint/Restore Mechanism by Hardware Assistance, IDP, 12/2018
  • Android-based Camera-supported Autonomous Overtaking utilizing Driving Simulator Data with OpenCV, Bachelor's Thesis, 08/2018
  • Android-based Camera-supported Lane Detection in Driving Simulator Data with OpenCV, Bachelor's Thesis, 08/2018
  • Analysis of the Structure of QEMU's Emulated ARMv7-A Architecture Using the Realview PBX-A9 Development Board, Bachelor's Thesis, 08/2018
  • Integration of heterogeneous compute resources under L4 Fiasco.OC and Genode OS Framework demonstrated exemplarily by utilizing a Co-Processor, IDP, 08/2018
  • Extending L4 Fiasco.OC/Genode OS by Capability Checkpoint/Restore, Bachelor's Thesis, 07/2018
  • Shallow Learning Based Schedulability Analysis for Migration of Software Components at Runtime, Master's Thesis, 07/2018
  • A guide to porting Fiasco.OC/Genode OS to (ARMv7-A) Cortex-A9 based Quad-Core single board computer, IDP, 06/2018
  • Extension of L4 Fiasco.OC/Genode by support for Real-Time Ethernet, Master's Thesis, 04/2018
  • Recurrent Neural Network Based Schedulability Analysis for Migration of Software Components at Runtime, Bachelor's Thesis, 04/2018
  • Extending L4 Fiasco.OC/Genode by Support for a FPGA-based RISC-V Co-Processor Allowing Hardware-Supported Snapshot Processing, Bachelor's Thesis, 04/2018
  • Development of a Redundant Memory Based Checkpoint/Restore Mechanism for L4 Fiasco.OC/Genode within the Robotic Domain, Master's Thesis, 04/2018
  • Extending Existing Memory Management Unit Concepts with Regard to Hardware Based Support for Checkpoint/Restore within L4 Fiasco.OC/Genode, Bachelor's Thesis, 03/2018
  • Extension of a Toolchain for Schedulability Analysis by a Task Generator Component for Evaluation of Different Real-Time Task Models, Bachelor's Thesis, 03/2018
  • Titel N/A, Fujitsu, Bachelor's Thesis, 03/2018
  • Android-based camera-supported road sign detection in driving simulator data with OpenCV, Bachelor's Thesis, 02/2018
  • Android-based camera-supported vehicle detection in driving simulator data with OpenCV, Bachelor's Thesis, 02/2018
  • Titel N/A, genua, Master's Thesis, 02/2018
  • Finalization of an Existing Migration Execution Process and Corresponding Performance Evaluation with Regard to Real-Time Behaviour, Master's Thesis, 02/2018

2017:

  • Extension of a Machine Learning Based Toolchain for Migration Planning by a Deep Learning Component, Bachelor's Thesis, 12/2017
  • Extension of a Monitoring Component for L4 Fiasco.OC/Genode, IDP, 12/2017
  • Synchronisation of the KIA4SM testbed, IDP, 09/2017
  • Android-based camera-supported object detection in driving simulator data with OpenCV, Bachelor's Thesis, 09/2017
  • Implementation of a MMU in FPGA based on the Xilinx Zynq-7000 SoC, Internship, 06/2017 - 09/2017
  • Development of a Multicore-supported incremental Checkpoint/Restore mechanism for L4 Fiasco.OC/Genode, Bachelor's Thesis, 08/2017
  • Development of a Multicore-supported Checkpoint/Restore mechanism for L4 Fiasco.OC/Genode supporting both full and partial snapshots, Bachelor's Thesis, 08/2017
  • Integration of an Android Smartphone as sensor-based input device for control of an automotive simulator, Bachelor's Thesis, 07/2017
  • Development of an intelligent, machine learning supported migration planning strategy in Genode, IDP, 06/2017
  • Development and Comparison of two different Checkpoint/Restore Mechanism for L4 Fiasco.OC/Genode, IDP, 02/2017

2016:

  • Extension of L4 Fiasco.OC/Genode by Management Mechanisms for Coexistent Scheduling Strategies on an Embedded Real-time Multicore System, IDP, 11/2016
  • Design and Prototypical Implementation of an OC-based Controller-Stack for Optimizing Mixed-Critical Thread Scheduling in L4 Fiasco.OC/Genode, Master's Thesis, 10/2016
  • Design and Prototypical Implementation of a High-Level Synchronization Component for Dynamic Updates of Task Run Queues in L4 Fiasco.OC/Genode, Master's Thesis, 10/2016
  • Design and Development of real-time capable Checkpoint/Restore mechanisms for L4 Fiasco.OC/Genode, Master's Thesis, 10/2016
  • Schedulability Analysis of Distributed Embedded Real-Time Systems with Regard to Automated Machine Learning Support, Bachelor's Thesis, 09/2016
  • Porting of an existing Linux-based Checkpoint/Restore Mechanism (CRIU) to L4 Fiasco.OC/Genode, Bachelor's Thesis, 04/2016
  • Port and Extension of a Toolchain Regarding Machine Learning Supported Schedulability Analysis in Distributed Embedded Real-Time Systems, Master's Thesis, 04/2016
  • Extension of L4 Fiasco.OC and Genode OS Framework by the Concept of a Distributed File System, Bachelor's Thesis, 03/2016
  • Comparison of the PikeOS Hypervisor and L4 Fiasco.OC/Genode: Development of a PikeOS Emulation Layer and Porting on Xilinx Zynq-7000 SoC, Master's Thesis, 03/2016
  • Extension of L4 Fiasco.OC and Genode OS Framework by the Concept of a Distributed Shared Memory, Bachelor's Thesis, 01/2016

2015:

  • Extension of the Genode OS Framework by a Component for Runtime-Monitoring of a Real-Time Operating System, Bachelor's Thesis, 12/2015
  • Design and prototypical implementation of a toolchain for offline task-to-machine mapping in distributed embedded systems, Master's Thesis, 10/2015
  • Design and implementation of an automotive networking testbed for a hybrid simulator, Master's Thesis, 10/2015
  • Examination of Different Strategies for Static and Dynamic Task Assignment in Distributed, Embedded, Real-Time Systems, Bachelor's Thesis, 09/2015
  • Analysis of Routing Protocols (in particular Wireless) and Publish/Subscribe-based Communication Paradigm regarding their Applicability in an Ethernet-based Mesh Network, Bachelor's Thesis, 09/2015
  • Design of an OC-based Method for efficient Synchronization of L4 Fiasco.OC Microkernel Tasks, Bachelor's Thesis, 06/2015
  • Design and development of a prototypical hybrid simulator for testing of self-adaptive automotive systems, IDP, 06/2015
  • Prototypical realization of a real-time Ethernet-based Intra-Vehicular Mesh Network implemented in a RC-Model-Car, IDP, 06/2015
  • Extension of the L4 Fiasco.OC Microkernel by a Module supporting the USB 2.0 Standard, Bachelor's Thesis, 05/2015
  • Extension of an Existing L4/Fiasco.OC Microkernel Component for Dynamic Task Management in Regard to Process Recovery and Scalability, IDP, 05/2015
  • Development of an interface for real-time data exchange and manipulation of the ns-3 network simulator, Bachelor's Thesis, 04/2015
  • Extension of the L4/Fiasco.OC Microkernel by a module for dynamic adaptation of the task execution order, Bachelor's Thesis, 04/2015
  • Extension of the L4/Fiasco.OC Microkernel by a module for Monitoring of a Real-Time System in Regard to Distributed Task-Planning, Bachelor's Thesis, 02/2015

2014:

  • Porting L4 to PowerPC with QEMU, IDP, 11/2014
  • Dynamic task management between interconnected L4 microkernel instances, Bachelor's Thesis, 10/2014
  • Developement of a Benchmark for the
    Evaluation of Different IPC Mechanisms on Embedded Multicore Systems, Fraunhofer ESK, Bachelor's Thesis, 09/2014
  • Reverse Engineering of a proprietary x86-library for the platform and media independent connection to an engine control unit, Bachelor's Thesis, 09/2014
  • Titel N/A, BMW, Master's Thesis, 06/2014
  • State-of-the-art analysis/evaluation of existing low-cost 802.11a hardware with regard to implementing the IEEE 802.11p standard, Bachelor's Thesis, 05/2014

2013:

  • Investigation and development of an app ecosystem for use in environments with high quality standards, Bachelor's Thesis, 11/2013

Forschungsgebiete

  • Software-based Online Reconfiguration [Process Migration, Checkpoint/Restore]
  • Distributed Embedded Real-Time Systems [Automotive]
  • L4 Microkernel [Fiasco.OC & Genode Operating System Framework]
  • Hybrid Simulation
  • HW/SW Co-Design (z.B. FPGA)
  • Machine Learning

Projekte

  • KIA4SM - Kooperative Integrationsarchitektur für zukünftige Smart Mobility Lösungen [BMBF/Software Campus, Siemens, 03/2015 - 10/2017]
  • MaLSAMi - Machine-Learning gestützte Schedulability Analyse für die Migration software-basierter Komponenten zur Laufzeit [BMBF/Software Campus, Huawei, 12/2017 - 04/2019]
  • HaCRoM - Hardware-gestützter Echtzeit Checkpoint/Restore-Mechanismus für die Migration von Software-Komponenten in L4-Mikrokern-basierten Betriebssystemen [BMBF/Software Campus, Huawei, 11/2018 - 10/2019]
  • TUM PREP 2019 - Hybrid Simulator Testbed for Autonomous Driving [06/2019 - 08/2019]

Publikationen

  • Sebastian Eckl, Daniel Krefft, Uwe Baumgarten: Migration of Components and Processes as means for dynamic Reconfiguration in Distributed Embedded Real-Time Operating Systems. OSPERT 2017, 2017 the 13th Annual Workshop on Operating Systems Platforms for Embedded Real-Time Applications mehr…
  • Christof Budnik, Sebastian Eckl and Marco Gario: A Hybrid Testbed for Verification of Cyber-physical Production Systems. 4th Int. Workshop on Applied Verification for Continuous and Hybrid Systems, 2017 mehr…
  • Daniel Krefft, Sebastian Eckl und Uwe Baumgarten: KIA4SM ‐ Kooperative Integrationsarchitektur für zukünftige Smart Mobility Lösungen. Gesellschaft für Informatik - Fachgruppe für Betriebssysteme, 2017, mehr…
  • Sebastian Eckl, Daniel Krefft, Uwe Baumgarten: COFAT 2015 - KIA4SM - Cooperative Integration Architecture for Future Smart Mobility Solutions. Conference on Future Automotive Technology, 2015 mehr…